The present invention relates generally to pipelined circuits, and more specifically to fast pipelined adder and compressor circuits.
Multiplication is one of the major operations in general purpose microprocessors and digital signal processors. The speed with which a multiplier circuit can operate often determines how fast a processor can be clocked.
A fast array multiplier is typically divided into two parts: a partial product summation tree, and a final adder. See G. Goto, T. Sato, M. Nakajima, and T. Sukemura, xe2x80x9cA 54xc3x9754 Regularly Structured Tree Multiplier,xe2x80x9d IEEE Journal of Solid State Circuits, p. 1229, Vol. 27, No. 9, September, 1992.
The partial product summation tree takes up a significant portion of the total multiplication delay and is typically implemented using full adders arranged as three-to-two (3:2) compressors and four-to-two (4:2) compressors. For a discussion of compressors, see Neil H. E. Weste and Kamran Eshragihan, xe2x80x9cPrinciples of CMOS VLSI Design: A Systems Perspective,xe2x80x9d 2nd Ed., pp. 554-558 (Addison Wesley Publishing YEAR). Increasing the speed of compressors can increase the speed of partial product summation trees, multipliers, and entire integrated circuits.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for fast compressor circuits.